1. Technical Field
This disclosure generally relates to packaging of integrated circuits and particularly relates to conductive bar systems useful in the production of package-on-package (PoP) semiconductor packages.
2. Description of the Related Art
Ongoing demand for smaller electronic devices has pressured manufacturers of such devices to increase the component density and reduce the component size wherever possible within the device. Integrated circuit manufacturers have responded by increasing the use of chip scale packaging and wafer level packaging techniques to minimize the footprint of the integrated circuit package, at times reducing the package to a size approaching the size of the semiconductor die itself through the use of direct surface mountable ball grid arrays and flip chip configurations.
The drive to reduce size is not without consequences, however. The reduced package size may render the distribution of solder balls on the semiconductor die itself physically impossible—for example where the resultant contact pad pitch would be less than the diameter of the solder balls used to in the ball grid array. One solution to accommodating ball grid arrays requiring a large number of contacts is through the use of a material or compound disposed about the periphery of the semiconductor die. The additional surface area thus provided permits the formation of a redistribution layer having an acceptable contact pad spacing or pitch. Such semiconductor packages are referred to as “fan out” wafer level packages or embedded wafer level ball grid array (eWLB) packages.
To further consolidate and conserve circuit board real estate semiconductor packages may also be vertically stacked to form a Package-on-Package (PoP) package. A PoP package is formed by stacking a top package (the “PoPt package”) on a bottom package (the “PoPb package”). In some PoP packages, electrical connections between the PoPt and PoPb packages are made between one or more contact pads on the lower surface of the PoPt package and one or more contact pads on the upper surface of the PoPb package fan out area, for example through the use of appropriate diameter solder balls disposed between the PoPt and PoPb semiconductor packages.
Physically, the PoPb package has a stepped appearance, with the fan out area at a lower height than the central area mold cap covering the semiconductor die. The height of the step in the PoPb package varies, but is generally on the order of a few tenths of a millimeter. The step height controls the minimum distance achievable between the PoPt and PoPb packages. Larger diameter solder balls are used to span the increased distance between the PoPt package and the fan out area of the PoPb package however, the use of larger solder balls to attach the PoPt package to the PoPb package effectively decreases the solder ball density (or, alternatively, limits the ball pitch) achievable on the PoPt package ball grid array. For example, where a 0.3 mm solder ball on a 0.5 mm pitch may be achievable between the PoPb package and the underlying substrate, the step height distance between the PoPb package and the PoPt package may require the use of a 0.5 mm solder ball on a pitch ranging from 0.6 mm to 0.85 mm.
Additional considerations in PoP packaging include the effects of thermal expansion, in particular, the differential thermal expansion between PoPt and PoPb packages and between the PoP package and the underlying substrate to which it is attached. Thermal cycling the PoP package can cause fatigue or stress cracks to form in the solder connections linking the various packages forming the PoP or between the PoP package and the circuit board to which the package is attached. The use of larger solder balls to span the distance between PoPt and PoPb packages exacerbates the issues by increasing the forces exerted on the solder connections. It is desirable, therefore, to provide a cost-effective and flexible solution for electrically coupling the semiconductor packages within a PoP package.